The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Dec. 21, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Peng Li, Hillsboro, OR (US);

William K. Lui, Portland, OR (US);

Sanjeev N. Trika, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/10 (2016.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/068 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 12/10 (2013.01); G06F 3/064 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/152 (2013.01); G06F 2212/214 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7203 (2013.01);
Abstract

Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.


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