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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10291394 B1

PDFFull Text
Date of Patent:
May. 14, 2019

Filed:

Oct. 01, 2015

Flexible architecture and instruction for advanced encryption standard (aes)

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shay Gueron, Haifa, IL;

Wajdi K Feghali, Boston, MA (US);

Vinodh Gopal, Westborough, MA (US);

Raghunandan Makaram, Northborough, MA (US);

Martin G Dixon, Portland, OR (US);

Srinivas Chennupaty, Portland, OR (US);

Michael Kounavis, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

NDWE, LLP

Primary Examiner:

Joseph P Hirl

Assistant Examiner:

Kalish K Bell

Int. Cl.
CPC ...
H04L 9/28 (2006.01); G06F 21/72 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); G06F 12/14 (2006.01); G06F 21/60 (2013.01); G06F 12/0875 (2016.01); G06F 9/30 (2018.01); G06F 12/0862 (2016.01); G06F 9/38 (2018.01); G11C 7/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0631 (2013.01); G06F 3/0623 (2013.01); G06F 3/0665 (2013.01); G06F 3/0689 (2013.01); G06F 9/30007 (2013.01); G06F 9/30036 (2013.01); G06F 9/30047 (2013.01); G06F 9/30145 (2013.01); G06F 9/30178 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3887 (2013.01); G06F 9/3895 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/1408 (2013.01); G06F 21/602 (2013.01); G11C 7/1072 (2013.01); H04L 9/0816 (2013.01); H04L 9/0861 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01); G06F 2212/452 (2013.01); G06F 2212/454 (2013.01); G06F 2212/602 (2013.01); H04L 2209/12 (2013.01); H04L 2209/24 (2013.01);
Abstract

A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a 'one round' pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

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