The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jan. 29, 2016
Applicant:

Csmc Technologies Fab2 Co., Ltd., Wuxi New District, CN;

Inventors:

Feng Huang, Wuxi New District, CN;

Guangtao Han, Wuxi New District, CN;

Guipeng Sun, Wuxi New District, CN;

Feng Lin, Wuxi New District, CN;

Longjie Zhao, Wuxi New District, CN;

Huatang Lin, Wuxi New District, CN;

Bing Zhao, Wuxi New District, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/76 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76229 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (), a first P well () and a channel region shallow trench isolating structure () are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (); performing photoetching and ion injection to form a second N well () in the first N well and form a second P well () in the first P well; forming a polysilicon gate () and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode () and a source electrode ().


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