The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Mar. 22, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Te Ho, Hsinchu, TW;

Shih-Yu Chang, Hsinchu, TW;

Da-Wei Lin, Hsinchu, TW;

Chien-Chih Chiu, Tainan County, TW;

Ming-Chung Liang, Hsin-chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/321 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76835 (2013.01); H01L 21/76877 (2013.01);
Abstract

Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.


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