The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jun. 14, 2017
Applicant:

Nuvoton Technology Corporation, Hsinchu Science Park, TW;

Inventors:

Aryeh Heilprin, Tel-Aviv, IL;

Rafael Eliezer Diaz, Caesarea, IL;

Arnon Sharlin, Herut, IL;

Assignee:

NUVOTON TECHNOLOGY CORPORATION, Hsinchu Science Park, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/00 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); H01L 27/0207 (2013.01); G06F 17/5031 (2013.01); G06F 17/5068 (2013.01); G06F 2217/06 (2013.01); G06F 2217/84 (2013.01);
Abstract

A method for designing an integrated circuit die, the method including generating a first layout for the die which includes at least one decap; and performing a post-processing decap insertion operation to add at least one additional decap in excess of the at least one decap, the operation including: for at least a portion of the first layout, identifying at least some of whichever locations in at least the portion have positive slack, as 'candidate' locations; and inserting at least one additional decap at at least one respective location from among the 'candidate' locations.


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