The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

May. 02, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Babita C. Verma, New Delhi, IN;

Parveen Khurana, Delhi, IN;

Sanjeev Azad, Haryana, IN;

Xin Gu, Austin, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/504 (2013.01);
Abstract

Disclosed herein are systems and methods to perform electrical analysis of a circuit design to verify electrical behavior and performance of the circuit design in a two-step process. Initially, a simulator transient analysis is performed on circuit blocks of a circuit design to obtain a current through each device path in each circuit block, and using the current obtained the IR drop and EM problems are examined to get EM-IR drop analysis. Next, a simulator transient analysis is performed on a top level circuit of a circuit design and current values generated in a first step to obtain EM-IR drop analysis for a full circuit design such that a circuit designer may debug, analyze and visualize various IR and EM value plots for circuit blocks and top level circuit of the circuit design together or separately.


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