The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jun. 30, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dorit Shapira, Atlit, IL;

Krishnakanth V. Sistla, Beaverton, OR (US);

Efraim Rotem, Haifa, IL;

Eric Distefano, Livermore, CA (US);

James G. Hermerding, II, Vancouver, WA (US);

Esfir Natanzon, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3024 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01); G06F 11/3058 (2013.01); G06F 11/3409 (2013.01); G01R 31/2856 (2013.01); G06F 2201/81 (2013.01); Y02D 10/126 (2018.01); Y02D 10/172 (2018.01);
Abstract

An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.


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