The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Oct. 26, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Peter Breun, Munich, DE;

Joachim Wehinger, Unterhaching, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03D 1/04 (2006.01); H04B 1/10 (2006.01); H04B 1/12 (2006.01); H04L 25/02 (2006.01); H04L 25/03 (2006.01); H04B 1/7107 (2011.01); H04J 11/00 (2006.01);
U.S. Cl.
CPC ...
H04B 1/1036 (2013.01); H04B 1/123 (2013.01); H04B 1/71072 (2013.01); H04J 11/004 (2013.01); H04L 25/0202 (2013.01); H04L 25/03006 (2013.01);
Abstract

A receiver for reducing an interference component in a receive signal is provided. The interference component is caused by a first interferer emitting payload data and a second interferer emitting only broadcast data for communication control. The receiver includes a first compensation circuit configured to generate a first compensation signal based on a component of the receive signal received from the first interferer. Further, the receiver includes a second compensation circuit configured to generate a second compensation signal based on only a-priori knowledge of at least one broadcast channel carrying the broadcast data, or based on a detection of symbols in the receive signal which represent the broadcast data. The detection of symbols is based on only the a-priori knowledge of the at least one broadcast channel. The receiver also includes a combination circuit configured to combine the receive signal, the first compensation signal and the second compensation signal.


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