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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10283625 B1

PDFFull Text
Date of Patent:
May. 07, 2019

Filed:

Dec. 08, 2017

Integrated strained stacked nanosheet fet

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Ramachandra Divakaruni, Ossining, NY (US);

Juntao Li, Cohoes, NY (US);

Xin Miao, Guilderland, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Vazken Alexanian

Primary Examiner:

Jarrett J Stark

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/7842 (2013.01); H01L 29/7843 (2013.01); H01L 29/7853 (2013.01); H01L 21/02274 (2013.01);
Abstract

Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.

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Quick Actions:

Cheng, Kangguo. (2019). Integrated strained stacked nanosheet fet (U.S. Patent No. 10283625). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10283625

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