The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Jun. 01, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Jongsun Sel, Los Gatos, CA (US);

Tuan Pham, San Jose, CA (US);

Mitsuteru Mushiga, Yokkaichi, JP;

Yoshihiro Ikeda, Yokkaichi, JP;

Daewung Kang, Milpitas, CA (US);

Akio Nishida, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/24 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 45/16 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.


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