The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Nov. 08, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Chien Liu, Taipei, TW;

Chao-Ching Hsieh, Tainan, TW;

Yu-Ru Yang, Hsinchu County, TW;

Hsiao-Pang Chou, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 21/02532 (2013.01); H01L 21/265 (2013.01); H01L 27/2463 (2013.01); H01L 29/0843 (2013.01); H01L 45/1206 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/1675 (2013.01); H01L 45/1608 (2013.01);
Abstract

The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.


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