The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Dec. 22, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ruilong Xie, Schenectady, NY (US);

Chanro Park, Clifton Park, NY (US);

Andre Labonte, Mechanicville, NY (US);

Lars Liebmann, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 29/66 (2006.01); H01L 23/535 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0332 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H01L 23/5329 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.


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