The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Mar. 27, 2015
Applicant:
Cavium, Inc., San Jose, CA (US);
Inventors:
Nimalan Siva, San Ramon, CA (US);
Premshanth Theivendran, Foster City, CA (US);
Kishore Badari Atreya, San Jose, CA (US);
Assignee:
Cavium, LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/10 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/105 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 15/7807 (2013.01);
Abstract
A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.