The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Dec. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David Won-jun Song, Chandler, AZ (US);

James R. Hastings, Chandler, AZ (US);

Akhilesh P. Rallabandi, Gilbert, AZ (US);

Morten S. Jensen, Messa, AZ (US);

Christopher Wade Ackerman, Phoenix, AZ (US);

Christopher R. Schroeder, Gilbert, AZ (US);

Nader N. Abazarnia, Chandler, AZ (US);

John C. Johnson, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/10 (2006.01); G01R 31/28 (2006.01); H05B 6/10 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2875 (2013.01); H05B 6/10 (2013.01);
Abstract

Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.


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