The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Dec. 02, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Pin-Dai Sue, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Li-Chun Tien, Tainan, TW;

Shun-Li Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0948 (2006.01); H03K 19/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H03K 19/21 (2013.01);
Abstract

A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region.


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Sue, Pin-Dai. (2019). Semiconductor device layout (U.S. Patent No. 10277227). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10277227

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