The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

May. 16, 2017
Applicant:

Ams Sensors Singapore Pte. Ltd., Singapore, SG;

Inventors:

Radoslaw Marcin Gancarz, Adliswil, CH;

Daniel Furrer, Uetikon am See, CH;

Miguel Bruno Vaello Paños, Zurich, CH;

Stephan Beer, Schaffhausen, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 17/89 (2006.01); H01L 27/148 (2006.01); H01L 27/146 (2006.01); H04N 13/207 (2018.01); H04N 13/254 (2018.01); H04N 13/271 (2018.01); G01S 7/486 (2006.01); G01S 7/491 (2006.01); H04N 5/374 (2011.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14831 (2013.01); G01S 7/4863 (2013.01); G01S 7/4915 (2013.01); G01S 17/89 (2013.01); H01L 27/14616 (2013.01); H01L 27/14623 (2013.01); H04N 5/374 (2013.01); H04N 5/378 (2013.01); H04N 5/3745 (2013.01); H04N 13/207 (2018.05); H04N 13/254 (2018.05); H04N 13/271 (2018.05);
Abstract

An imaging device, including a monolithic semiconductor integrated circuit substrate, comprises a focal plane array of pixel cells. Each one of the pixel cells includes a gate overlying a region of the substrate operable to convert incident radiation into charge carriers. The pixel also includes a CMOS readout circuit including at least one output transistor in the substrate. The pixel further includes a charge coupled device section on the substrate adjacent the gate, the charge coupled device section including a sense node to receive charge carriers transferred from the region of the substrate beneath the gate. The sense node is coupled to the output transistor. The pixel also includes a reset switch coupled to the sense node. The pixel's charge coupled device section has a buried channel region. The pixel also includes one or more bias enabling switches operable to enable a bias voltage to be applied to the gate. At least one of the reset switch or the one or more bias enabling switches is formed in the buried channel region.


Find Patent Forward Citations

Loading…