The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jun. 25, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Hsin-Wen Chen, Kaohsiung, TW;

Chi-Chang Shuai, Hsinchu, TW;

Hsien-Hung Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/11 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/24 (2013.01);
Abstract

The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.


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