The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Apr. 17, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Weibo Yu, Hsinchu, TW;

Jui-Ping Chuang, Hsinchu, TW;

Chen-Hsiang Lu, Hsinchu, TW;

Shao-Yen Ku, Jhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/302 (2006.01); H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3157 (2013.01); H01L 21/0206 (2013.01); H01L 21/02019 (2013.01); H01L 21/0226 (2013.01); H01L 21/02057 (2013.01); H01L 21/02203 (2013.01); H01L 21/67703 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate. The method includes forming a protective layer over the surface of the semiconductor substrate in a first chamber after the first process. The method includes performing a first transferring process to transfer the semiconductor substrate from the first chamber into a substrate carrier. The method includes performing a second transferring process to transfer the semiconductor substrate from the substrate carrier into a second chamber. The semiconductor substrate is located in the substrate carrier during a substantially entire first time interval between the first transferring process and the second transferring process. The method includes removing the substantially entire protective layer in the second chamber. The method includes performing a second process over the surface of the semiconductor substrate.


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