The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Aug. 17, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Yong-Liang Li, Singapore, SG;

Hao Su, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/82385 (2013.01); H01L 21/823835 (2013.01); H01L 27/0928 (2013.01); H01L 29/0653 (2013.01); H01L 29/42376 (2013.01); H01L 29/4916 (2013.01);
Abstract

A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.


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