The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jun. 30, 2017
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Guan Huei See, Singapore, SG;

Yu Gu, Singapore, SG;

Arvind Sundarrajan, Singapore, SG;

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6836 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 24/11 (2013.01); H01L 24/12 (2013.01); H01L 2224/0401 (2013.01);
Abstract

Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.


Find Patent Forward Citations

See, Guan. (2019). Method and apparatus for wafer level packaging (U.S. Patent No. 10276424). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10276424

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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