The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jul. 07, 2017
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventor:

Chun-Hung Lin, Hsinchu, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); G11C 17/16 (2006.01); G11C 11/419 (2006.01); G11C 17/18 (2006.01); G06F 21/73 (2013.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/24 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0054 (2013.01); G06F 21/73 (2013.01); G11C 7/062 (2013.01); G11C 7/12 (2013.01); G11C 7/24 (2013.01); G11C 11/419 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract

A memory cell includes a latch, two antifuse elements, and two select transistors. The latch is connected with a first node and a second node, and receives a first power voltage and a second power voltage. The latch is selectively enabled or disabled according to an enable line voltage. The first antifuse element is connected with the first node and an antifuse control line. The second antifuse element is connected with the second node and the antifuse control line. The gate terminal, the first drain/source terminal and the second drain/source terminal of the first select transistor are connected with a word line, the first node and a bit line, respectively. The gate terminal, the first drain/source terminal and the second drain/source terminal of the second select transistor are connected with the word line, the second node and an inverted bit line, respectively.


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