The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Feb. 09, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
John MacLaren, Austin, TX (US);
Carl Olson, Austin, TX (US);
Jerome J. Johnson, Cedar Park, TX (US);
Thomas J. Shepherd, Cedar Park, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.