The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Oct. 10, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Po-Yu Chen, Baoshan Township, TW;

Wan-Hua Huang, Hsinchu, TW;

Jing-Ying Chen, Taipei, TW;

Kuo-Ming Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/0653 (2013.01); H01L 29/1087 (2013.01); H01L 29/456 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01);
Abstract

A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.


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