The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

May. 16, 2017
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Peter Almern Losee, Clifton Park, NY (US);

Alexander Bolotnikov, Niskayuna, NY (US);

Stacey Joy Kennerly, Niskayuna, NY (US);

James William Kretchmer, Ballston Spa, NY (US);

Assignee:

GENERAL ELECTRIC COMPANY, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/36 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/0865 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.


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