The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Nov. 20, 2017
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Yu-Ru Yang, Hsinchu County, TW;
Chih-Chien Liu, Taipei, TW;
Chao-Ching Hsieh, Tainan, TW;
Hsiao-Pang Chou, Taipei, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 29/0847 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/1683 (2013.01);
Abstract
The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.