The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Oct. 12, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jia-Ming Lin, Hsinchu, TW;

Wei-Ken Lin, Tainan, TW;

Shiu-Ko JangJian, Tainan, TW;

Chun-Che Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/31105 (2013.01); H01L 21/31155 (2013.01); H01L 21/76224 (2013.01); H01L 22/12 (2013.01); H01L 29/785 (2013.01); H01L 29/7846 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01);
Abstract

A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.


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