The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Dec. 09, 2016
Silicon Storage Technology, Inc., San Jose, CA (US);
The Regents of the University of California, Oakland, CA (US);
Xinjie Guo, Goleta, CA (US);
Farnood Merrikh Bayat, Goleta, CA (US);
Dmitri Strukov, Goleta, CA (US);
Nhan Do, Saratoga, CA (US);
Hieu Van Tran, San Jose, CA (US);
Vipin Tiwari, Dublin, CA (US);
Silicon Storage Technology, Inc., San Jose, CA (US);
The Regents Of The University Of California, Oakland, CA (US);
Abstract
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.