The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Jun. 28, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ashish Ranjan, West Lafayette, IN (US);

Vivek Kozhikkottu, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0862 (2016.01); G06F 12/0842 (2016.01); G06F 12/0866 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 12/0842 (2013.01); G06F 12/0866 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/312 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6022 (2013.01); G11C 2207/107 (2013.01);
Abstract

An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.


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