The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Dec. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei Wu, Portland, OR (US);

Brian J. Hickmann, Sherwood, OR (US);

Dennis R. Bradford, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/00 (2006.01); H03M 13/13 (2006.01); H03M 13/15 (2006.01); H03M 13/27 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/13 (2013.01); H03M 13/15 (2013.01); H03M 13/1575 (2013.01); H03M 13/616 (2013.01); H03M 13/27 (2013.01);
Abstract

An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.


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