The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Sep. 14, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Shin-Cheng Lin, Tainan, TW;

Yeh-Jen Huang, Hsinchu, TW;

Fu-Hsin Chen, Jhudong Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0921 (2013.01); H01L 29/0623 (2013.01); H01L 29/0642 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/405 (2013.01); H01L 29/7823 (2013.01);
Abstract

A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.


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