The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2019
Filed:
Oct. 17, 2016
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Evelyn Napetschnig, Diex, AT;
Ulrike Fastner, Villach, AT;
Alexander Heinrich, Bad Abbach, DE;
Thomas Fischer, Villach, AT;
Assignee:
INFINEON TECHNOLOGIES AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/308 (2006.01); H01L 21/683 (2006.01); H01L 21/268 (2006.01); H01L 21/304 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/268 (2013.01); H01L 21/304 (2013.01); H01L 21/3086 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/02205 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/03912 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/05005 (2013.01); H01L 2224/0566 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05657 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/05669 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/11009 (2013.01); H01L 2224/11011 (2013.01); H01L 2224/11019 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11845 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13105 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13118 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/26125 (2013.01); H01L 2224/27009 (2013.01); H01L 2224/27019 (2013.01); H01L 2224/2746 (2013.01); H01L 2224/2747 (2013.01); H01L 2224/27845 (2013.01); H01L 2224/291 (2013.01); H01L 2224/29007 (2013.01); H01L 2224/29013 (2013.01); H01L 2224/29105 (2013.01); H01L 2224/29109 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29116 (2013.01); H01L 2224/29118 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/94 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01049 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01); H01L 2924/206 (2013.01); H01L 2924/2064 (2013.01);
Abstract
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
Napetschnig, Evelyn. (2019). Semiconductor devices and methods of forming thereof (U.S. Patent No. 10262959). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10262959
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile