The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Dec. 27, 2017
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Wayne F. Ellis, Jericho Center, VT (US);

Wayne S. Richardson, Saratoga, CA (US);

Akash Bansal, Santa Clara, CA (US);

Frederick A. Ware, Los Altos Hills, CA (US);

Lawrence Lai, San Jose, CA (US);

Kishore Ven Kasamsetty, Cupertino, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/406 (2006.01); G11C 7/02 (2006.01); G11C 7/20 (2006.01); G11C 11/4072 (2006.01); G11C 29/02 (2006.01); G06F 1/3234 (2019.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G06F 1/3234 (2013.01); G11C 7/02 (2013.01); G11C 7/20 (2013.01); G11C 11/4072 (2013.01); G11C 11/4074 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01);
Abstract

In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.


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