The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Oct. 10, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yong-hee Park, Hwaseong-si, KR;

Young-seok Song, Hwaseong-si, KR;

Ji-soo Chang, Seoul, KR;

Young-chul Hwang, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01);
Abstract

An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.


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