The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Oct. 27, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Fu-Hsin Chen, Jhudong Township, TW;

Yung-Hao Lin, Jhunan Township, TW;

Shin-Cheng Lin, Tainan, TW;

Hsin-Chih Lin, Hsinchu, TW;

Chia-Ching Huang, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 31/0256 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 29/20 (2006.01); H01L 29/207 (2006.01); H01L 29/423 (2006.01); H01L 23/31 (2006.01); H01L 29/66 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 23/3171 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01); H01L 29/42364 (2013.01); H01L 23/291 (2013.01); H01L 23/293 (2013.01); H01L 29/66462 (2013.01);
Abstract

A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.


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