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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10256252 B1

PDFFull Text
Date of Patent:
Apr. 09, 2019

Filed:

Dec. 13, 2017

Three-dimensional memory device containing structurally reinforced pedestal channel portions and methods of making the same

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventor:

Junpei Kanazawa, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Eva Y Montalvo

Assistant Examiner:

Kevin Quinto

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02233 (2013.01); H01L 21/02274 (2013.01); H01L 21/02636 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 29/1037 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer include a second silicon oxide material having a greater density than the first silicon oxide material.

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