The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Aug. 25, 2017
Applicant:

Monterey Research, Llc, Santa Clara, CA (US);

Inventors:

Yukio Hayakawa, Fukushima-ken, JP;

Hiroyuki Nansei, Fukushima-ken, JP;

Assignee:

MONTEREY RESEARCH, LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 27/115 (2017.01); H01L 27/11521 (2017.01); H01L 27/11568 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 23/528 (2006.01); H01L 27/11517 (2017.01); H01L 27/11563 (2017.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 23/5283 (2013.01); H01L 27/115 (2013.01); H01L 27/11517 (2013.01); H01L 27/11521 (2013.01); H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/42332 (2013.01); H01L 29/42348 (2013.01); H01L 29/66757 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.


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