The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Mar. 16, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Javier A. Falcon, Chandler, AZ (US);

Ye Seul Nam, Chandler, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Roman Caudillo, Portland, OR (US);

James S. Clarke, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 39/04 (2006.01); H01L 23/16 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/16 (2013.01); H01L 24/83 (2013.01); H01L 39/045 (2013.01); H01L 2224/29109 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32052 (2013.01); H01L 2224/32055 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01049 (2013.01);
Abstract

Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.


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