The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Jun. 12, 2016
Applicant:

Nexperia B.v., AB Nijmegen, NL;

Inventors:

Shun Tik Yeung, Hong Kong, HK;

Pompeo V. Umali, Hong Kong, HK;

Chi Ho Leung, Hong Kong, HK;

Kan Wae Lam, Hong Kong, HK;

Hans-Juergen Funke, Hamburg, DE;

Shu-Ming Yip, Hong Kong, HK;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/373 (2006.01); H05K 1/02 (2006.01); H05K 7/10 (2006.01); H05K 7/20 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/373 (2013.01); H01L 23/49562 (2013.01); H01L 24/00 (2013.01); H05K 1/0204 (2013.01); H05K 1/0207 (2013.01); H05K 1/0209 (2013.01); H05K 7/10 (2013.01); H05K 7/209 (2013.01);
Abstract

A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.


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