The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Apr. 03, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Dechao Guo, Niskayuna, NY (US);

Liyang Song, Mount Kisco, NY (US);

Xinhui Wang, Poughkeepsie, NY (US);

Qintao Zhang, Mount Kisco, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/82385 (2013.01); H01L 21/823456 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/42376 (2013.01); H01L 29/4983 (2013.01); H01L 29/7856 (2013.01);
Abstract

A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.


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