The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Mar. 11, 2016
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Duc Huynh, San Jose, CA (US);

Jiayong Le, Santa Clara, CA (US);

Ayhan Mutlu, Santa Clara, CA (US);

Peivand Tehrani, Campbell, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 2217/10 (2013.01); G06F 2217/84 (2013.01);
Abstract

A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.


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