The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Jun. 01, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Florian Eckardt, Dresden, DE;

Zhibin Yu, Unterhaching, DE;

Qing Xu, Unterhaching, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); G06F 11/18 (2006.01); G06F 11/14 (2006.01); H03M 13/25 (2006.01); H03M 13/39 (2006.01); H03M 13/41 (2006.01);
U.S. Cl.
CPC ...
G06F 11/18 (2013.01); G06F 11/1479 (2013.01); H03M 13/256 (2013.01); H03M 13/3994 (2013.01); H04L 1/0054 (2013.01); H03M 13/41 (2013.01);
Abstract

The disclosure relates to a decoding device, comprising: a receiver configured to provide a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code; a trellis generation logic configured to generate a plurality of trellis states based on the sequence of information bits and the channel code; a trellis reduction logic configured to reduce the plurality of trellis states by at least one trellis state based on the context redundancy information; and a decoder configured to decode the sequence of information bits by using a metric based on the reduced number of trellis states.


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