The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2019
Filed:
Apr. 06, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Hiroshi Yanagigawa, Ibaraki, JP;
Assignee:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H01L 21/823487 (2013.01); H01L 27/0266 (2013.01); H01L 27/088 (2013.01); H01L 29/0634 (2013.01); H01L 29/36 (2013.01); H01L 29/7813 (2013.01); H03K 17/6874 (2013.01); H03K 17/06 (2013.01);
Abstract
A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.