The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

May. 25, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Hironobu Miyamoto, Ibaraki, JP;

Tatsuo Nakayama, Ibaraki, JP;

Atsushi Tsuboi, Ibaraki, JP;

Yasuhiro Okamoto, Ibaraki, JP;

Hiroshi Kawaguchi, Ibaraki, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1087 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42364 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 29/7787 (2013.01); H01L 29/1066 (2013.01); H01L 29/41758 (2013.01); H01L 29/4236 (2013.01); H01L 29/452 (2013.01);
Abstract

Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.


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