The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2019
Filed:
May. 10, 2018
Applicant:
Murata Manufacturing Co., Ltd., Kyoto-fu, JP;
Inventors:
Assignee:
Murata Manufacturing Co., Ltd., Kyoto-fu, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01); H01L 27/082 (2006.01); H01L 29/205 (2006.01); H01L 29/417 (2006.01); H01L 29/737 (2006.01); H01L 21/8222 (2006.01); H01L 21/8252 (2006.01);
U.S. Cl.
CPC ...
H01L 27/082 (2013.01); H01L 21/8252 (2013.01); H01L 23/66 (2013.01); H01L 27/0605 (2013.01); H01L 27/0658 (2013.01); H01L 29/045 (2013.01); H01L 29/0692 (2013.01); H01L 29/0817 (2013.01); H01L 29/205 (2013.01); H01L 29/41708 (2013.01); H01L 29/66242 (2013.01); H01L 29/737 (2013.01); H01L 29/7371 (2013.01); H03F 1/0238 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H01L 21/8222 (2013.01); H01L 29/0821 (2013.01); H03F 2200/451 (2013.01);
Abstract
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.