The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Jun. 06, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Sudeep Mandal, Bangalore, IN;

Sebastian T. Ventrone, South Burlington, VT (US);

Richard S. Graf, Gray, ME (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/26 (2013.01); H01L 21/56 (2013.01); H01L 23/481 (2013.01); H01L 24/10 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01);
Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.


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