The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Dec. 15, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Nicolas Degors, Le Versound, FR;

Shawn P. Fetterolf, Cornwall, VT (US);

Ahmet S. Ozcan, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 21/321 (2006.01); H01L 21/3205 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/02532 (2013.01); H01L 21/02614 (2013.01); H01L 21/26513 (2013.01); H01L 21/31155 (2013.01); H01L 21/321 (2013.01); H01L 21/324 (2013.01); H01L 21/32055 (2013.01); H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 21/76243 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01);
Abstract

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.


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