The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Jan. 27, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Tapan Jyoti Chakraborty, San Diego, CA (US);

Roberto Fabian Averbuj, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G01R 31/28 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G01R 31/2856 (2013.01); G11C 29/022 (2013.01); G11C 29/04 (2013.01); G11C 29/38 (2013.01); G11C 29/44 (2013.01); G11C 29/32 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/1208 (2013.01); G11C 2029/3202 (2013.01);
Abstract

An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.


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