The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Jan. 04, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mohammad Abdallah, El Dorado Hills, CA (US);

Ravishankar Rao, Redwood City, CA (US);

Karthikeyan Avudaiyappan, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 3/00 (2006.01); G06F 13/12 (2006.01); G06F 12/00 (2006.01); G06F 15/00 (2006.01); G06F 12/0864 (2016.01); G06F 12/0862 (2016.01); G06F 12/0811 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 9/30058 (2013.01); G06F 9/3802 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 2212/452 (2013.01);
Abstract

A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.


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