The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Dec. 29, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Suleyman Sair, Chandler, AZ (US);

Kshitij A. Doshi, Chandler, AZ (US);

Charles R. Yount, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G06F 11/07 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/3861 (2013.01); G06F 9/455 (2013.01); G06F 11/0745 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/1629 (2013.01); G06F 11/1641 (2013.01); G06F 9/30189 (2013.01); G06F 9/30196 (2013.01); G06F 9/3889 (2013.01); G06F 11/1608 (2013.01); G06F 15/8007 (2013.01);
Abstract

Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.


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