The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Dec. 06, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jennifer Chin, Sungai Ara, MY;

Su Wei Lim, Klang, MY;

Poh Thiam Teoh, Penang, MY;

Ting Lok Song, Bayan Lepas, MY;

Sun Zheng E, Balik Pulau, MY;

Say Cheong Gan, Bukit Mertajam, MY;

Sujea Lim, Bintangor, MY;

Ming Yi Lim, Ayer Itam, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/3287 (2019.01); G06F 1/16 (2006.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01); G06F 1/3218 (2019.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/1626 (2013.01); G06F 1/3206 (2013.01); G06F 1/3218 (2013.01); G06F 1/3243 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01); Y02D 10/151 (2018.01); Y02D 10/152 (2018.01);
Abstract

Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.


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